Apparatus for computing square roots



April 2l, 1970 R. A. CLIFF APPARATUS FOR COMPUTING SQUARE ROOTS FiledNOV. 50. 1966 LIB -2 sheets-sheevt 1 Rodger A.Cliff M@ ATTORNEYS April21, 1970 R. A. cLlr-F 3,508,039

APPARATUS FOR COMPUTING SQUARE'ROOTS lla- 2T INVENTOR Rodger A. Cliff YY1 INHIBIT IA-l L. 1- -ll1-2 lA-3 x BY 904415' e7 M ATTORNEYS UnitedStates Patent O 3,508,039 APPARATUS FOR COMPUTING SQUARE ROOTS Rodger A.Clil, College Park, Md., assignor to the United States of America asrepresented by the Administrator of the National Aeronautics and SpaceAdministration Filed Nov. 30, 1966, Ser. No. 598,119 Int. Cl. G06f 7/38U.S. Cl. 23S-158 6 Claims ABSTRACT OF THE DISCLOSURE Apparatus forobtaining a square root of a number wherein two binary registers areselectively interconnected by gates so that a numerical progression issubtracted from one register which contains a number the square root ofwhich is desired.

The invention described herein was made by an employee of the UnitedStates Government and may be manufactured and used by or for theGovernment for governmental purposes without the payment of any royaltythereon or therefor.

The necessity for determining the square root of numbers is well known.For many numbers the square root obtained from a table of square rootsor from mathematical computations is an approximation of the exactsquare root of the number. The closeness of the approximation isdetermined by the use to which the square root is to be put. In manysituations an approximation to the nearest integer is satisfactory; thisinvention is concerned with such an approximation. That is, thisinvention provides apparatus for approximating the square root of anumber to the nearest integer.

The prior art has utilized various methods and apparatus for obtainingthe square root of numbers. Analog methods, combinational logic matrixmethods, and Newton approximation methods have been used. However, theseapproaches have not always been entirely satisfactory. In general, themethods are complicated and the apparatus for carrying out the methodsare equally complicated. In addition, prior art apparatus usesadditional components to obtain the square root of a number, therebyadding to the possibility of computer system failure. Further, theaddition of components increases the size and weight of the computer;and the addition of components adds to the power used by the computer.In many environments increased power consumption, reduced reliability,added components, and added weight and size are undesirable; in otherenvironments they are critically undesirable. Specically, when acomputer is located on board a spacecraftor in other remoteenvironments-these items become critical to the operation of the craft.In fact, generally speaking, any system that uses more than the minimumnumber of components is less than the most desirable system for use on aspacecraft. Hence, because spacecraft computers must obtain the squareroot of numbers to perform certain calculations, it is desirable toprovide a method and apparatus for taking the square root of a numberthat uses less power and fewer components, is lighter and smaller, andis more reliable than prior art devices.

It is an object of this invention to provide a new apparatus forcomputing the square root of a number.

It is also an object of this invention to provide a new and improvedapparatus for obtaining the square root of a number to the nearestinteger which does not require the use of a separate system forobtaining the square root.

It is a still further object of this inventionto provide a new andimproved apparatus for obtaining the square Iooot of a number that issimple and uncomplicated, small and lightweight and reliable.

ICC

While the peculiar advantages of the apparatus of the invention ashereinafter described make the invention primarily suitable for use on aspacecraft, the invention is more general and is useful in determiningthe square root of numbers in earthbound electronic systems as well.

In accordance with a principle of the invention, the apparatusaccomplishes the results by sequentially subtracting a numericalprogression of numbers from a number whose square root is desired;detecting when the result of the sequential subtractions is one of a setof predetermined numbers (for example either zero or a negative number);and counting the number of subtractions that have taken place when oneof the set of predetermined numbers (for example zero or a negativenumber) is reached. The number of subtractions is equal to the squareroot of the number to the nearest integer.

In accordance with a further principle of the invention an exemplaryapparatus comprises two binary counting means, a coupling means, andpulse inhibiting means. The rst binary counting means counts in aforward direction and the second binary counting means counts in abackward direction. The stages of the forward counting means areselectively coupled to the stages of the backward counting means throughthe coupling means so that the number in the forward counting means canbe subtracted from the number in the backward counting means in apredetermined manner. Finally, the inhibit means is connected to theforward and backward counting means, the coupling means, and a pulsesource so that it passes pulses from the pulse source to the forwardcounting means until the number in the backward counting means becomeseither zero or a negative number.

In operation, the number whose square root is desired is inserted intothe backward counting means. The forward counting means is cleared andpulses are applied to both it and the coupling means. When the rst pulseis applied the forward counting means generates an output. The outputpasses through the coupling means and causes a subtraction from thebackward counting means. The number subtracted is equal to the iirstnumber in the numerical progression determined by the method of theinvention. When the second pulse is applied, the forward counting meansgenerates a second output. This second output passes through thecoupling means and causes a subtraction of the second number in thenumerical progression from the backward counter. This subtraction of thenext number in the progression continues to occur for each subsequentinput pulse until the number in the backward counting means equalseither zero or a negative number. When the zero or negative numbercondition occurs the inhibit means prevents the further application ofpulses. And, in accordance with the method of the invention, the numberof pulses counted by the forward counting means is equal to the squareroot of the number originally in the backward counter to the nearestinteger.

It will be appreciated that the invention provides a. simple apparatusfor determining the square root'of va number to the nearest integer. Themethod simply involves the subtraction of a numerical progression ofnumbers from the desired number and the counting of the number ofsubtractions performed to obtain the square root of the number. Theapparatus of the invention is simple and includes two conventionalbinary counting means, one forward counting and the second backwardcounting, a coupling means and an inhibiting means. By placing thenumber in the backward counting means, pulsing the forward countingmeans and sequentially subtracting the output of the forward countingmeans from the backward counting means until the backward counterreaches zero or a negative number, the square root of the numberoriginally in the backward counter is easily obtained.

The foregoing objects and many of the attendant advantages of thisinvention will become more readily appreappreciated as the same becomesbetter understood by reference to the following detailed descriptionwhen taken in conjunction with the accompanying drawings wherein:

FIG. 1 is a block diagram illustrating the general form of theinvention;

FIG. Z is a block diagram more specifically illustrating one embodimentof the invention; and

FIG. 3 is a block diagram illustrating a second embodiment of theinvention.

For ease of illustration, in the following description N represents thesquare root of the number M where both M and N are integers.

In accordance with the theory of the invention N approximately equalsthe square root of M provided that N satisfies the following relation 11 1/ M N S M -l- These inequalities may be rewritten separately as:

Abm-

The integer N that satisfies both of these equations may be determinedby successively testing positive integers (starting at zero) until thecorrect integer is determined. In other words, for a specific M,integers can be substituted for N until the foregoing inequalities aresatisfied. That integer will be the square root of M to the nearestinteger.

Further, in accordance with another aspect of the inventions theory, byworking from zero towards successively larger integers it is onlynecessary to satisfy the second inequality set forth above. That is, ifan N is found that satisfies www;

as the value of the integers being tested increases by 1, then thatinteger necessarily satisfies the inequality NSM-r Hence, in accordancewith this aspect of the inventions theory, only the second inequalityillustrated above is used.

In taking the square root, one starts With M rather than VM The secondinequality, which can also be written 1 N i m can be expressed in termsof M rather than the VM, by squaring both sides. Specifically, if

Further, since M and N are both defined as integers, this expression isequivalent to NZ-i-N. Hence, N2+N M is the equation used to find the\/M, where N is equal to M to the nearest integer.

It is well known that a squared number can be made equal to aprogression of numbers. Specifically,

More generally,

N N 2= E 2K 1) Because N2 can be described as a progression of numbers,N24-N can also be described as a progression of numbers. Specifically,

equal to the M to the nearest integer.

Hence, in accordance with the invention, the square root of a number tothe nearest integer can be obtained by performing the following steps onthat number:

(1) sequentially subtracting a progression of numbers from the numberwhose square root is desired;

(2) detecting when one of the sequential subtractions causes theremainder to equal either zero or a negative number; and

(3) counting the number of subtractions that have occurred when theremainder is zero or a negative number.

The number of subtractions is equalto N and, hence, is equal to thesquare root of the number M to the nearest integer.

FIGS. l, 2 and 3 illustrate embodiments of the apparatus of theinvention that will perform the foregoing steps. lor ease of discussion,all illustrated embodiments of the invention include a four-stageforward counter and a nine-stage backward counter. However, the four andnine stages are only by way of example and it is to be understood thatany number of stages can be used depending upon the size of the numberswhose square roots are desired.

FIG. 1 comprises a forward binary counter designated as A with its fourstages designated as 1A-1, 1A-2, 1A-3, and 1A-4; and a backward binarycounter designated as B with its nine stages designated as 1B-1, 1B-2,1B3, 1B-4, lB-S, 1B-6, .1B-7, 1B-8 and 1B-9. In addition t0 thecounters, the apparatus illustrated in FIG. 1 includes an inhibitcircuit 11, and a coupling circuit comprising four two-input AND gatesdesignated as A-1, A-Z, A-3 and A-4.

Each stage of the counter is a binary stage having a true :and acomplementary output designated as X and respectively. As is well knownin the art, when one output is a binary 1 the other output is a binary 0and vice versa. Further, the outputs switch binary states for each 0 tol input transition, but not for a 1 to 0 transition.

An input terminal 13, adapted for connection to a pulse source, isconnected to the input of the inhibit circuit 11. The output of theinhibit circuit is connected to the input of 1A-1 and through a timedelay to one input of each of the four AND gates. The output of 1A-1 isconnected to the input of 1A-2; the of lA-Z is connected to the input of1A-3; and the output of 1A-3 is connected to the input of 1A-4. The Xoutput of 1A-1 is connected to the second input of A-1; the X output of1A-2 is connected to the second input of A-2, the X output of 1A--3` isconnected to the input of A-3; and the X output of 1A-4 is connected tothe second input of A-4. In addition, the X output of 1A-1 is connectedto an output terminal 115, the X output of 1A2 is connected to outputterminal 17; the X output of 1A-3 is connected to an output terminal 19and the X output of 1A-4 is connected to an output terminal 2.1. Theoutput terminals, therefore, represent the outputs of the X sides of theA counter stages and, in the hereinafter description, are read from leftto right. Because the outputs are taken from from the X side of thestages and because the X outputs of one stage are connected to the inputof the subsequent stage the A counter is a forward counter.

The input of 1B-1 is connected to an input terminal 25. The X output ofeach lower order stage of the B counter is connected to the input of thenext higher order stage of the B counter in the same manner that the Acounters stages are interconnected. Hence, the stage interconnectionwill not be more fully described.

The output of A-1 is connected as a separate input to 1B-2; the outputof A-2 is connected as a separate input to 1B-3; the output of A-3 isconnected as a separate input to 1B-4; and the output of A4 is connectedas a separate input to lB-S. While the outputs from the AND gates areillustrated and described as separate inputs to their respective Bcounter stages they are not actually separate inputs. That is, in anactual embodiment of the device, isolation diodes are contained in theinput lines from the previous stage and from the AND gates; however, theactual terminals of the inputs to the stages are at the same point.Hence, a to 1 transition of either input operates to trigger a stage andchange its state.

The X outputs of the B counter are connected to output terminals asfollows: 1B-1 to 27 1B-2 to 29; 1B-3 to 31; 1B-4 to 33; lB-S to 35; 1B-6to 37; 1B-7 to 39; and 1B-8 is connected to terminal 41; while the Xoutput of 1B-9 is connected to the inhibit input of the inhibitingcircuit 11. Because the outputs of the B counter stages are taken fromthe X side and because the X side of a lower order stage is connected tothe input of the next higher order stage, the B counter is a backwardcounter. That is, the B counter subtracts the numerical value of anyparticular stage from the number in the counter each time that stage istriggered. Specically, each time stage 1B-1 is switched the decimalnumber l is subtracted from the number in counter B; each time 1B-2 isswitched, the equivalent of a decimal 2 is subtracted; each time 1B-3 isswitched a 4 is subtracted and so on through all nine stages of counterThe system illustrated in FIG. 1 operates to carry out the invention bysubtracting from a number located in counter B the numerical progression2-l-4-i-6, etc. That is, each time an input pulse is applied to counterA it subtracts the next number in the progression from the nurnber thenin counter B. Specically, the irst input pulse to counter A generates a1000 at counter As output terminals 15, 17, 19 and 21; however, this rstpulse subtracts 2 from counter B because counter B is a backward counterand because the output of the rst stage of counter A is connected to theinput of the second stage of counter B. More specifically, when 1A-1 istriggered, its X output goes from 0 to l. This passes through gate A-1and triggers 1B-2 which is the second stage of counter B and correspondsin value to the decimal 2. Hence, a 2 is subtracted from counter B. Whenthe second pulse is applied to counter A, 1A-1 shifts to its oppositestate, i.e., its X output goes to 0 and its X output goes to l. When theX output of 1A-1 goes to 1, 1A-2l is triggered so that its X output goesfrom 0 to 1 and its X output goes from 1 to 0. The 1 X output of 1A-2 issubsequently gated by A-Z and triggers 1B-3. 1B-3 is the third stage ofcounter B, corresponding to decimal 4; hence 4 is subtracted fromcounter B for the second pulse to counter A.

The systems illustrated in FIGS. 2 and 3 are similar to i FIG. 1 andoperate in a manner identical to the operation of that system. Thesesystems, however, also include a time delay means. This is includedbecause a switching pulse from both the previous stage and a switchingpulse from an AND gate can be applied to a B counter stage at the sametime to thereby create an error. That is, if

6 A-Z and 1B-2 both presented a switch pulse to 1B-3 at the same time,lB-I:` would interpret them as a single input and would only switch oncerather than twice, as it should. By providing suitable time delaysystems of the type illustrated in FIGS. 2 and 3 this error can beprevented.

FIG. 2 is identical to FIG. 1 with the addition of a first time delayTD-l between 1B-2 and 11B-3; a second time delay TD-2r between 1B-3 and1B-4; and a third time delay 'ID-3 between 11B-4 and lB-S. These timedelays provide a settle down period ybetween the application of pulsesfrom the AND gates and the subsequent switching of higher order Bcounter stages by lower o-rder B counter stages. The operation of FIG. 2is otherwise identical to the operation of the FIG. 1 embodiment.

FIG. 3 is also identical to FIG. 1 with the addition of an alternativetype of time delay system. In FIG. 3 a time delay system 43 is connectedbetween the inhibit gate output and the inputs to the two input ANDgates. The time delay system is connected so that, for each input pulseto terminal 13, a gating pulse is rst provided to AND gate A-4, then toAND gate A-3, then to AND gate A-Z and iinally to AND gate A-l. The timedelay system, therefore, also prevents the simultaneous application ofpulses to the B counters stages by providing for a settle down timebetween the application of pulses from the AND gates and the applicationof pulses from lower order B counter stages to higher order B counterstages. Hence, as with the FIG. 2 embodiment, this time delay settledown period prevents errors.

Turning now to an example of the complete operation of the systemillustrated in FIG. 2; assume the decimal number 59 is contained inregister B. The decimal number 59 is represented by the binary number110111000 at the output terminals of counter B, as read from left toright. This number can be placed in counter B, for example, by applyingpulses to counter Bs input terminal 25 until counter Bs output terminalsreached this binary number.

.Prior to operation, counter A is cleared by means not shown so that allof its X outputs are equal to 0. When a first pulse is applied to inputterminal 13 it passes through the inhibit gate and triggers the Acounter stage 1A-1. The lA-ll X output goes from 0 to 1 and the X outputgoes from 1 to 0. The X output of 1A-1 is subsequently gated through A-1and triggers 1B-2. When 1B-2 is triggered its X output goes from 1 to 0;because its X output drops from 1 to 0 it does not trigger 1B-3 and atthis point the B output is 100111000. This is equivalent to the decimalnumber 57. Hence, the iirst number in the progression2has beensubtracted from the 59 originally contained in counter B.

The second pulse switches 1A-1 to its opposite state; that is, its Xoutput goes from 0 to 1 and its X output goes from 1 to 0. The X outputof 1A-1 then triggers 1A-2 to change its X output from 0 to l and its Xoutput from l to 0. At this point the X outputs from the A counter atterminals 15, 17, 19 and 2.1 are 0100. The 1 output of 1A-2 is gated to1B-3 by A-Z and triggers 1B-3. When 1B-3 is triggered its X output goesfrom 0 to 1. When its X output goes from 0` to 1 it triggers 1B-4 andthe X output of 1B-4 goes from 1 to 0. The X output of lB-rt does nottrigger 1B-5 and hence the output at this point is 101011000; this isequivalent to the decimal number 53. Hence, the second number in theprogression-4-has been subtracted from the previous 57 or an overall 6has been subtracted from the initial 59.

When the third input pulse triggers lA-l its X output changes to l andthe output from the A counter is 1100. Then the X output of 1A-1 isgated by A-1 to lB-Z and triggers 1B-2 changing 1B-2s X output from 0to 1. Also the l output of lA-Z is gated by A-2` to 1B-3 and triggers1B-3 changing 1B-3s X output from 1 to 0. The change of 1B-3s X outputfrom 1 to 0 has no effect on 11B-4 or any of the following stages.However, the to 1 change of 1B-2s output now reaches 1B-3 through timedelay TD-l and causes -1B-3 to change from a 0 to a 1. This secondchange in 1B-3 triggers 11B-4 to switch its output to a l. The 1 outputof `1B-4 triggers 1B-5 to cause its output to reduce to zero. At thispoint, the binary output of counter B is 111101000; this is equal to thedecimal number 47. Hence, the third number in the progression-6-has beensubtracted from 53.

The fourth pulse to counter A provides an output from counter A of 0010.This output in the manner described above triggers counter B so that itgenerates an output of 111001000. This binary number is equal to 39.

The fifth pulse provides an output of counter A that is 1010. Thisoutput passes through the AND gates to trigger the appropriate stages ofcounter B to cause counter B to generate an output of 101110000. Thisbinary number is equal to the decimal number 29.

The sixth pulse provides an output from counter A of 0110. This outputtriggers counter B to generate an output of 100010000. This output isequivalent to the decimal number 17.

The -seventh pulse to counter A changes its output to 1110. This outputtriggers counter B to generate a binary output of 110000000. This outputis equivalent to the decimal number 3.

The eighth pulse triggers counter A to generate an output of 0001. Thisoutput triggers counter B to generate an output of 110011111. The firsteight stages of this output represent a modulo 28 negative number whilethe ninth stage merely detects whether a zero or negative number hasbeen reached. Hence the output of 1B-9` applies a signal to the inhibitinput of inhibit circuit 11 to inhibit the further application of pulsesto both the AND gates and the A counter.

Prior to the generation of the inhibit pulse, however, eight pulses werecounted by counter A; hence, the closest numerical integer representingthe square root of 59 is 8. A brief check with a slide rule or with asquare root table determines that the square root of 59 is approximately7.68. Hence 8 is the nearest integer to the square root of 59.

In conclusion, the system illustrated in FIG. 2 acts to subtract thesequence 2-1-4-5-6 etc. from the number contained in counter B untileither a zero or a negative number is in counter B. This situationinhibits the further application of pulses through the inhibit gate 11because the output of stage 1B-9 becomes 1. The output from counter A atthis point represents the square root of the number originally containedin the counter B to the nearest integer.

It will be appreciated by those skilled in the art and others that theinvention provides apparatus for obtaining the square root of a numberto the nearest integer. Specifically, the steps require the sequentialsubtraction of a progression of numbers from the number whose squareroot is desired. When the subtraction reaches either zero or a negativenumber the number of subtractions performed is equal to the square root.Further, the invention provides an equally simple apparatus for carryingout the method.

The apparatus includes two counters: one for counting up and the otherfor counting down. The for-Ward counter sequentially subtracts numbersfrom the backward counter in a predetermined manner. When the backwardcounter reaches either zero or a negative number, the apparatus preventsfurther counting of pulses by the forward counter and the number ofpulses counted by 3S the forward counter at that point is equal to thesquare root of the number originally in the backward counter.

It will further be appreciated that the four stage up ward counter andthe nine stage backward counter are discussed only by way of example.Any number of stages for each counter can be used depending upon thesize of the numbers whose square roots are desired. Similarly, the timedelay means illustrated in FIGS. 2 and 3 are also only by way ofexample. Other suitable time delay means can be utilized to provide thesame function. Moreover, it will be appreciated by those skilled in theart that the progression 2-\4+6, etc. is only by way of example. Anyprogression that will suitably determine the desired result can be used.

Moreover, this invention can be used to take the square root ofnoninteger numbers. For example, suppose B is a n-ary number with lessthan 2P n-ary places in the fractional part, then M (1121 XB is aninteger and Nw\/1T=11P Therefore, VBQJIL-PXN. Hence, the invention maybe practiced otherwise than as specifically described herein.

What is claimed is:

1. Apparatus for computing the square root of a number comprising:

a first binary means having a plurality of stages for counting pulses;

a second binary means having a plurality of stages for storing a binarynumber;

an inhibit means for inhibiting the application of pulses and having aninput adapted for connection to a pulse source, an output connected tosaid first binary means and an inhibit input connected to said secondbinary means; and

a coupling means for connecting the outputs of said plurality of stagesof said rst binary means to the inputs of predetermined stages of saidplurality of stages of said second binary means.

2. Apparatus as claimed in claim 1 wherein said second binary means is asecond binary counter and wherein the output of the last stage isconnected to the inhibit input of said inhibit means.

3. Apparatus as claimed in claim 2 wherein said coupling means includesa plurality of AND gates each of which has at least two inputs, whereinone input of each AND gate is connected to the output of one stage ofsaid iirst binary counter and a second input of each stage is connectedto the output of said inhibit means and the output of each AND gate isconnected to one stage of said second binary counter in a predeterminedmanner.

4. Apparatus as claimed in `claim 3 wherein the output of each stage ofsaid first binary counter is connected ythrough an AND gate to the inputof the next higher order stage of said second binary counter.

5. Apparatus as claimed in claim 4 including time delay lmeans connectedbetween predetermined stages of said second binary counter.

6. Apparatus as claimed in claim 4 including a time delay meansconnected between said inhibit means and the second input of said ANDgates.

References Cited UNITED STATES PATENTS 3,267,267 8/1966 Clark 23S-158 XEUGENE G. BOTZ, Primary Examiner R. S. DILDINE, JR., Assistant ExaminerU.S. Cl. X.R. 235--175

